> The high-level design is proprietary too.

They have source code files for their 'Freedom' core designs up on GitHub under an Apache 2.x license. These can be directly used to evaluate their designs as FPGA soft-cores.

The SoC, with the Rocket core used. This is very different from SiFive's own U series cores, which are proprietary.

SiFive has E-series (aka "Freedom Everywhere") and U-series (aka "Freedom Unleashed") cores, both of which seem to be based on Rocket. And they do provide high-level designs for both on their GitHub, under a free license.

High-level designs of the SoC, not of those cores themselves is public for some platforms.

Based on whatever for the core doesn't matter, as the cores themselves in any case diverge quite a lot from Rocket.

This is not correct. Anyone can design and build a RISC-V CPU without ever getting permission from anyone.

Anything that uses the ARM ISA on the other hand requires a (costly) licence from ARM.

SiFive has its own proprietary *implementation" buty that's not required, and there are many free open source implementations.

I wrote SiFive CPUs, not RISC-V there. (because this BeagleV board uses SiFive)

There's a _huge_ gap between academic implementations and ones that are actually worth shipping. I can see RISC-V winning quite handily for microcontrollers. But on anything bigger than that...

Western Digital's open sourced SweRV cores are approximately the same performance as the closed-source SiFive 7-series ones.

The main difference is the WD cores are 32 bit, no MMU, probably DTIM rather than cache (not sure).

The guts of the dual issue decode, register file, pipeline is there, which is the hard part. The other bits could be relatively easily added by the open source community, probably cribbing components from RocketChip.

People said that about open source compilers. Where are we now?

You need to give it a few years before you write it off. It's significant that most CS/EE students are now learning the RISC-V architecture.

They aren't for the customers of SiFive. What is your greater point with this comment? That SiFive isn't Open Source or that they are equivalent to Arm?

This video from SiFive clearly explains the RISC-V ecosystem and how SiFive is involved.

https://www.youtube.com/watch?v=CmGIJMYwWNw

Arm provides Verilog source code of their CPU cores for their customers. It's an industry standard practice.